HY5S7B6LF-H 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

Hynix Semiconductor

Description

512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No.0.1 0.2 0.3 0..
and Figures Final Version History Draft Date Oct.

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Datasheet Specifications

Part number: HY5S7B6LF-H
Manufacturer: Hynix Semiconductor
File Size: 709.96 KB
Datasheet: HY5S7B6LF-H_HynixSemiconductor.pdf
Description: 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst

Applications

* which requires large memory density and high bandwidth. It is organized as 4banks of 8,388,608x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data

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HY5S7B6LF-H 512MBit MOBILE SDR SDRAMs based 4Bank x16I Hynix Semiconductor

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