* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst
HY5S7B6LFP-S Datasheet (709.96 KB)
HY5S7B6LFP-S
Hynix Semiconductor
709.96 KB
512mbit mobile sdr sdrams based on 8m x 4bank x16i/o.
512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0..
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