ICS543 Datasheet - ICST

ICS543 PRELIMINARY INFORMATION Clock Divider and 2X Multiplier

The ICS543 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 90 MHz at 5.0 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 3, 5, 6, or 10, or a multiply by 2 of the input clock. There a.

ICS543 Features

* Packaged in 8 pin SOIC

* Low cost clock divider and 2X multiplier

* Low skew (500ps) outputs. One is ÷ 2 of other.

* Easy to use with other generators and buffers

* Input clock frequency up to 90 MHz at 5 V

* Output clock duty cycle of 45/55

ICS543_ICST.pdf