ICS541 Datasheet - ICST

ICS541 PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on th.

ICS541 Features

* Packaged in 8 pin SOIC

* Low cost clock divider

* Low skew (500ps) outputs. One is ÷ 2 of other.

* Easy to use with other generators and buffers

* Input clock frequency up to 135 MHz at 3.3 V

* Input clock frequency up to 156 MHz at 5.0 V

* T

ICS541_ICST.pdf

ICS541 Datasheet Preview — Preview of ICS541 PDF

Datasheet Details

Part number:

ICS541

Manufacturer:

ICST

File Size:

77.44 KB

Description:

Preliminary information pll clock divider.

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ICS541 ICS541 PRELIMINARY INFORMATION PLL Clock Divider ICST

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