ICS9LP525-2 - 56-pin CK505 Clock
PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus.
Before configuring this pin as a Clock Request Pin, the P
ICS9LP525-2 Features
* 2 - CPU differential low power push-pull pairs
* 7- SRC differential low power push-pull pairs
* 1 - CPU/SRC selectable differential low power push-pull pair
* 1 - SRC/DOT selectable differential low power push-pull pair
* 5 - PCI, 33MHz
* 1 - PCI_F
