IS61DDSB21M36A - 36Mb DDR-II (Burst 2) SIO SYNCHRONOUS SRAM
The 36Mb IS61DDSB21M36A and IS61DDSB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have a separate I/O bus.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the Timing Reference
IS61DDSB21M36A Features
* 1Mx36 and 2Mx18 configuration available.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Seperate I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write input ports.
