IS61LPD102418A Features
* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth expansion and address pipelining
IS61LPD102418A_IntegratedSiliconSolution.pdf
Datasheet Details
IS61LPD102418A
Integrated Silicon Solution
251.04 KB
512k x 36/ 1024k x 18 18mb synchronous pipelined / double cycle deselect static ram.
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IS61LPD102418A Distributor
