* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth expansion and address pipelining
IS61LPD51236A Datasheet (251.04 KB)
IS61LPD51236A
Integrated Silicon Solution
251.04 KB
512k x 36 - 1024k x 18 18mb synchronous pipelined double cycle deselect static ram.
IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
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