* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth expansion and address pipelining
IS61LPD51218A Datasheet (253.24 KB)
IS61LPD51218A
Integrated Silicon Solution
253.24 KB
256k x 36 - 512k x 18 9 mb synchronous pipelined double cycle deselect static ram.
IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
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