MT48LC128M4A2, MT48LC32M16A2 Datasheet (Micron Technology)

MT48LC128M4A2, MT48LC32M16A2, (MT48LCxxMxxA2) SYNCHRONOUS DRAM

The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Each of the x4’s 134,217,728-bit banks is organize

MT48LC128M4A2 Features

* PC100- and PC133-compliant

* Fully synchronous; all signals registered on positive edge of system clock

* Internal pipelined operation; column address can be changed every clock cycle

* Internal banks for hiding row access/precharge

* Programmable burst leng