MT48LC16M16LFBG - 256M x 16 Mobile SDRAM
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the x16’s 67,108,864-bit banks is organized
MT48LC16M16LFBG Features
* Temperature Compensated Self Refresh (TCSR)
* Fully synchronous; all signals registered on positive edge of system clock
* Internal pipelined operation; column address can be changed every clock cycle
* Internal banks for hiding row access/precharge
* Progra
