* Features
* PC100- and PC133-compliant
* Fully synchronous; all signals registered on positive edge of system clock
* Internal, pipelined operation; column address can be changed every clock cycle
* Internal banks for hiding row access/precharge
* Programmabl
MT48LC16M8A2 Datasheet (3.64 MB)
MT48LC16M8A2
Micron Technology
3.64 MB
4 meg x 8 x 4 banks sdr sdram.
SDR SDRAM
MT48LC32M4A2
* 8 Meg x 4 x 4 Banks MT48LC16M8A2
* 4 Meg x 8 x 4 Banks MT48LC8M16A2
* 2 Meg x 16 x 4 Banks
128Mb: x4.
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