MT4LC8M8E1 Datasheet - Micron Technology

MT4LC8M8E1 DRAM

The 8 Meg x 8 DRAMs are high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits organized in a x8 configuration. The 8 Meg x 8 DRAMs are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 8,192 rows by 1,0.

MT4LC8M8E1 Features

* Single +3.3V ±0.3V power supply

* Industry-standard x8 pinout, timing, functions, and packages

* 13 row, 10 column addresses (E1) or 12 row, 11 column addresses (B6)

* High-performance CMOS silicon-gate process

* All inputs, outputs and clocks are LVTTLcompa

MT4LC8M8E1_MicronTechnology.pdf