* a 25mV offset and 40-µV/°C drift. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). FEATURES LOW DRIFT | V GS1‐2 / T| ≤40µV/°C LOW LEAKAGE IG = 10pA TYP. LOW NOISE en = 8nV/√Hz TYP. LOW OFFSET V
LS842
Micross
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Low drift monolithic dual jfet.
LS842 MONOLITHIC DUAL N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS842 is a high-performance monolithic dual .
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