MPC951 Datasheet (Motorola) - (MPC950 / MPC951) LOW VOLTAGE PLL CLOCK DRIVER

MPC951, (MPC950 / MPC951) LOW VOLTAGE PLL CLOCK DRIVER

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs.

With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs.

The devices employ a fully differential PLL design to minimize cycle to cycle and long term jitter.

This parameter is of significant importance when the clock driver is

MPC951 Features

* allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition, the external feedback allows for a wider variety of input

* to

* output frequency relationships. The MPC951 REF_SEL pin allows for the selection of an alternate LVCMOS input clock to be used as a test c