Datasheet4U Logo Datasheet4U.com

74AUP2G79

Low-power dual D-type flip-flop

74AUP2G79 Features

* I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000

74AUP2G79 General Description

The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device e.

74AUP2G79 Datasheet (146.02 KB)

Preview of 74AUP2G79 PDF

Datasheet Details

Part number:

74AUP2G79

Manufacturer:

NXP ↗ Semiconductors

File Size:

146.02 KB

Description:

Low-power dual d-type flip-flop.
www.DataSheet4U.com 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 02

* 19 March 2008 Product data sheet 1. General des.

📁 Related Datasheet

74AUP2G79 - Low-power dual D-type flip-flop (nexperia)
74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 11 — 3 December 2020 Product data sheet 1. General description The 74AUP2G79.

74AUP2G79-Q100 - Low-power dual D-type flip-flop (nexperia)
74AUP2G79-Q100 Low-power dual D-type flip-flop; positive-edge trigger Rev. 3 — 3 December 2020 Product data sheet 1. General description The 74AUP.

74AUP2G00 - Low-power dual 2-input NAND gate (NXP)
74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NA.

74AUP2G00 - DUAL NAND GATE (Diodes)
NEW PRODUCT 74AUP2G00 DUAL NAND GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power an.

74AUP2G00 - Low-power dual 2-input NAND gate (nexperia)
74AUP2G00 Low-power dual 2-input NAND gate Rev. 11 — 9 June 2022 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND .

74AUP2G00-Q100 - Low-power dual 2-input NAND gate (nexperia)
74AUP2G00-Q100 Low-power dual 2-input NAND gate Rev. 2 — 9 June 2022 Product data sheet 1. General description The 74AUP2G00-Q100 provides dual 2-in.

74AUP2G02 - DUAL NOR GATE (Diodes)
NEW PRODUCT 74AUP2G02 DUAL NOR GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and.

74AUP2G02 - Low-power Dual 2-input NOR Gate (NXP)
74AUP2G02 Low-power dual 2-input NOR gate Rev. 7 — 4 February 2013 Product data sheet 1. General description The 74AUP2G02 provides a dual 2-input N.

TAGS

74AUP2G79 Low-power dual D-type flip-flop NXP Semiconductors

Image Gallery

74AUP2G79 Datasheet Preview Page 2 74AUP2G79 Datasheet Preview Page 3

74AUP2G79 Distributor