Datasheet4U Logo Datasheet4U.com

PCK2509SA Datasheet - NXP

PCK2509SA_PhilipsSemiconductors.pdf

Preview of PCK2509SA PDF
PCK2509SA Datasheet Preview Page 2 PCK2509SA Datasheet Preview Page 3

Datasheet Details

Part number:

PCK2509SA

Manufacturer:

NXP ↗

File Size:

79.03 KB

Description:

50-150 mhz 1:9 sdram clock driver.

PCK2509SA, 50-150 MHz 1:9 SDRAM clock driver

The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

The PCK2509SA opera

PCK2509SA Features

* Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications

* JEDEC compliant operation

* PLL reamins locked when outputs are disabled. adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via

📁 Related Datasheet

📌 All Tags

NXP PCK2509SA-like datasheet