* Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, th
PCK2510SA Datasheet (78.22 KB)
PCK2510SA
78.22 KB
50-150 mhz 1:10 sdram clock driver.
INTEGRATED CIRCUITS
PCK2510SA 50
*150 MHz 1:10 SDRAM clock driver
Product specification ICL03
* PC Motherboard ICs; Logic Products Gro.
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