PCK2510SL Datasheet (NXP) - 50-150 MHz 1:10 SDRAM clock driver

PCK2510SL, 50-150 MHz 1:10 SDRAM clock driver

The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

The PCK2510SL opera

PCK2510SL Features

* Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, th