* Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications
* When outputs are disabled, the PLL and feedback output are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2
PCK2509SL Datasheet (79.62 KB)
PCK2509SL
79.62 KB
50-150 mhz 1:9 sdram clock driver.
INTEGRATED CIRCUITS
PCK2509SL 50
*150 MHz 1:9 SDRAM clock driver
Product specification ICL03
* PC Motherboard ICs; Logic Products Grou.
📁 Related Datasheet
PCK2509S 50-150 MHz 1:9 SDRAM clock driver (NXP)
PCK2509SA 50-150 MHz 1:9 SDRAM clock driver (NXP)
PCK2510S 50-150 MHz 1:10 SDRAM clock driver (NXP)
PCK2510SA 50-150 MHz 1:10 SDRAM clock driver (NXP)
PCK2510SL 50-150 MHz 1:10 SDRAM clock driver (NXP)
PCK2000 CK97 66/100MHz System Clock Generator (NXP)
PCK2001 14.318-150 MHz I2C 1:18 Clock Buffer (NXP)
PCK2002 0-300 MHz I2C 1:18 clock buffer (NXP)
PCK2010 CK98 100/133MHz Spread Spectrum System Clock Generator (NXP)
PCK2010R CK98R 100/133MHz RCC spread spectrum system clock generator (NXP)
