PCK2509SL Datasheet (NXP) - 50-150 MHz 1:9 SDRAM clock driver

PCK2509SL, 50-150 MHz 1:9 SDRAM clock driver

The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

The PCK2509SL opera

PCK2509SL Features

* Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications

* When outputs are disabled, the PLL and feedback output are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2