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DS99R103 (DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

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Description

DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer April 2007 DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serialize.
The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

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Datasheet Specifications

Part number
DS99R103
Manufacturer
National Semiconductor
File Size
913.87 KB
Datasheet
DS99R103_NationalSemiconductor.pdf
Description
(DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

Features

* pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
* Internal DC Balancing encode/decode
* Supports AC

Applications

* LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects All LVCMOS inputs and control pins have internal pulldown On-chip filters for PLLs on Transmitter a

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