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DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS90C124 Description

DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2006 DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Seriali.
The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

DS90C124 Features

* pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. n User selectable clock edge for parallel data on both Transmitter and Receiver n Internal DC Balancing encode/decode
* Supports AC-coup

DS90C124 Applications

* n LOCK output flag to ensure data integrity at Receiver side n Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side n PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects n All LVCMOS inputs and control pins have internal pulldown n On-chip filters for PLLs on Tra

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Datasheet Details

Part number
DS90C124
Manufacturer
National Semiconductor
File Size
926.26 KB
Datasheet
DS90C124_NationalSemiconductor.pdf
Description
5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer National Semiconductor
National Semiconductor DS90C124-like datasheet