Description
DS99R101, DS99R102 www.ti.com SNLS240D * MARCH 2007 * REVISED APRIL 2013 DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializ.
The DS99R101/DS99R102 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
Features
* 1
* 2 3 MHz
* 40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions
* User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
* Internal DC Balancing Encode/Decode
* Supports AC-Coupling Interface with No External Coding Req
Applications
* LOCK Output Flag to Ensure Data Integrity at Receiver Side
* Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
* PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
* All LVCMOS Inputs and Control Pins Have Internal Pulldown
