* Ts may be safely operated into an inductive load; however, snubbing reduces switching losses. td(off) = RG Ciss In (VGG/VGSP) C, CAPACITANCE (pF) C, CAPACITANCE (pF) 800 VDS = 0 V VGS = 0 V 700 Ciss 600 TJ = 25°C 500 400 Crss Ciss 300 200 Coss 100 Crss 0 10 5 0 5 10 15 20 25 VGS VDS GATE
MTB2N60E Datasheet (260.49 KB)
MTB2N60E
260.49 KB
High energy power fet.
MTB2N60E Designer’s™ Data Sheet TMOS E FET.™ High Energy Power FET D2PAK for Surface Mount N Channel Enhancement Mode Silicon.
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