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MTB9N25E High Energy Power FET

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Description

MTB9N25E Designer’s™ Data Sheet TMOS E *FET.™ High Energy Power FET D2PAK for Surface Mount N *Channel Enhancement *Mode Silicon .

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Features

* d to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally sn

Applications

* that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced TMOS E
* FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain
* to
* source diode with a

MTB9N25E Distributors

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