* d to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally sn
MTB9N25E Datasheet (284.10 KB)
MTB9N25E
284.10 KB
High energy power fet.
MTB9N25E Designer’s™ Data Sheet TMOS E FET.™ High Energy Power FET D2PAK for Surface Mount N Channel Enhancement Mode Silicon .
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