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NB6L11S Input to LVDS Fanout Buffer/Translator

NB6L11S Description

NB6L11S VOLTAGE (130 mV/div) 2.5 V 1:2 AnyLevel] Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 clock or data receiver a.
Pin Name I/O Description 1 Q0 LVDS Output Non. inverted D output.

NB6L11S Features

* Input Clock Frequency > 2.0 GHz
* Input Data Rate > 2.5 Gb/s
* RMS Clock Jitter
* 0.5 ps, Typical
* 622 Mb/s Data Dependent Jitter
* 6 ps, Typical
* 380 ps Typical Propagation Delay
* 120 ps Typical Rise and Fall Times
* Single

NB6L11S Applications

* The NB6L11S has a wide input common mode range from GND + 50 mV to VCC
* 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6L11S is ideal for translating a variety of differential or single
* ended Clock or Data signals to 350 mV typical LVDS output lev

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ON Semiconductor NB6L11S-like datasheet