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NB6N11S Input to LVDS Fanout Buffer/Translator

NB6N11S Description

NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator .
The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS.

NB6N11S Features

* Maximum Input Clock Frequency > 2.0 GHz
* Maximum Input Data Rate > 2.5 Gb/s
* 1 ps Maximum of RMS Clock Jitter
* Typically 10 ps of Data Dependent Jitter
* 380 ps Typical Propagation Delay
* 120 ps Typical Rise and Fall Times
* Functionally

NB6N11S Applications

* The NB6N11S has a wide input common mode range from GND + 50 mV to VCC
* 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6N11S is ideal for translating a variety of differential or single
* ended Clock or Data signals to 350 mV typical LVDS output lev

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Input LVDS Fanout Buffer Translator ON Semiconductor
ON Semiconductor NB6N11S-like datasheet