MN3881S Datasheet (Panasonic Semiconductor) - PAL-Compatible CCD Video Signal Delay Element

MN3881S, PAL-Compatible CCD Video Signal Delay Element

CCD Delay Line Series MN3881S PAL-Compatible CCD Video Signal Delay Element Overview The MN3881S is a CCD signal delay element for video signal processing applications.

It contains such components as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits.

When the switch pin is grounded, the MN3881S samples the input using the supplied

MN3881S Features

* Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for color signal converted to low frequency. ( TOP VIEW ) SOP016-P-0225 Applications VCRs 1 MN3881S Block Diagram CCD Delay Line Series 12 4 Auto bias circuit VINC 16 Charge input block Charge de