* High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications. Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank. Allow Clock Input to have Spread Spectrum modulation
PI6C2516 Datasheet (298.63 KB)
PI6C2516
Pericom Semiconductor Corporation
298.63 KB
Phase-locked loop clock driver with 16 clock outputs.
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