PI6C2516 Datasheet - Pericom Semiconductor Corporation

PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs

The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any clock ou.

PI6C2516 Features

* High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications. Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank. Allow Clock Input to have Spread Spectrum modulation

PI6C2516_PericomSemiconductorCorporation.pdf