K4S560832C Datasheet - Samsung semiconductor

K4S560832C 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

The K4S560832C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock c.

K4S560832C CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Sept. 2001 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Sept. 2001 K4S560832C Revision History Revision 0.0 (Mar. 06, 2001) Revision 0.1 (Sep. 06, 2001) CMOS SDRAM Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also suppo.

K4S560832C Features

* JEDEC standard 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

* All inputs are

K4S560832C Datasheet (113.09 KB)