K4S561632D Datasheet - Samsung semiconductor

K4S561632D 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

The K4S561632D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock.

www.DataSheet4U.com K4S561632D CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL DataSheet4U.com DataShee Revision 0.1 Aug. 2002 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Aug. 2002 DataSheet4U.com DataSheet4U.com www.DataSheet4U.com K4S561632D Revision History Revision 0.0 (Jan., 2002) -First generation CMOS SDRAM Revision 0.1(Aug.,2002) - ICC6 of Low power is changed from 1.0 to 1.5 due to typo. et4.

K4S561632D Features

* JEDEC standard 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

* All inputs are

K4S561632D Datasheet (158.60 KB)