K4S640832C Datasheet | Samsung Semiconductor

CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Oct. 1999 - Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Oct.1999 Revision History Revision 0.1 (Oct. 02, 1999) - Changed misprinted speed bining from -75 to -70. CMOS SDRAM Rev.0.1 Oct.1999 2M x 8Bit x 4 Banks Synchronous DRAM Features - - - - JEDEC standard 3.3V power supply LVTTL patible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive...