K7A161831B, K7A163631B Datasheet - Samsung semiconductor

K7A161831B - 18MB B-DIE SYNC SRAM SPECIFICATION 100TQFP WITH PB / PB-FREE

The K7A163631B and K7A161831B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter.

K7A163631B K7A161831B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVI.

K7A161831B Features

* Synchronous Operation.

* 2 Stage Pipelined operation with 4 Burst.

* On-Chip Address Counter.

* Self-Timed Write Cycle.

* On-Chip Address and Control Registers.

* VDD= 2.5 or 3.3V +/- 5% Power Supply.

* 5V Tolerant Inputs Except I/O Pins.

K7A163631B_Samsungsemiconductor.pdf