Datasheet4U Logo Datasheet4U.com

K4M511633E-L - 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA

Description

The K4M511633E is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

  • 3.0V or 3.3V power supply.
  • LVCMOS compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
  • EMRS cycle with address key programs.
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • Special Function Support. -. PAS.

📥 Download Datasheet

Datasheet preview – K4M511633E-L

Datasheet Details

Part number K4M511633E-L
Manufacturer Samsung Semiconductor
File Size 112.42 KB
Description 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
Datasheet download datasheet K4M511633E-L Datasheet
Additional preview pages of the K4M511633E-L datasheet.

📁 Similar Datasheet

  • K4M511633C - 8M x 16Bit x 4 Banks Mobile SDRAM (Samsung semiconductor)
  • K4M51163LC - 8M x 16Bit x 4 Banks Mobile SDRAM (Samsung semiconductor)
  • K4M51163LE - 8M x 16Bit x 4 Banks Mobile SDRAM (Samsung semiconductor)
  • K4M51163PC-x - 8M x 16Bit x 4 Banks Mobile SDRAM (Samsung semiconductor)
  • K4M51163PI - 512Mb I-die Mobile SDR SDRAM (Samsung semiconductor)
  • K4M513233C - 4M x 32Bit x 4 Banks Mobile SDRAM (Samsung semiconductor)
  • K4M51323LC-F - Mobile-SDRAM (Samsung semiconductor)
  • K4M51323LC-G - Mobile-SDRAM (Samsung semiconductor)
  • K4M51323LC-L - Mobile-SDRAM (Samsung semiconductor)
  • K4M51323LC-SDN - Mobile-SDRAM (Samsung semiconductor)
Other Datasheets by Samsung

Full PDF Text Transcription

Click to expand full text
K4M511633E - Y(P)C/L/F 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 3.0V or 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25°C ~ 70°C). • 1 /CS Support. • 2chips DDP 54Balls FBGA with 0.
Published: |