Description
Serial Clock (SCL) The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.
Features
- Data EEPROM internally organized as 128/256 bytes and 16/32 pages × 8 bytes.
- Low power CMOS.
- VCC = 2.7 to 5.5 V operation.
- Two wire serial interface bus, I2C-Bus compatible.
- Filtered inputs for noise suppression with Schmitt trigger.
- Clock frequency up to 400 kHz.
- High programming flexibility.
- Internal programming voltage.
- Self timed programming cycle including erase.
- Byte-write and page-write programming,.
SLX24C0816_SiemensSemiconductorGroup.pdf