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SiS5591/5592 Pentium PCI A.G.P. Chipset
1. SiS5591/5592 SiS5595 OVERVIEW
SiS5591/5592 SiS5595
PCI A.G.P. & CPU Memory Controller PCI SYSTEM I/O
The SiS5591/5592 SiS5595 glueless P5 A.G.P. chipset provides a high performance/cost index Desktop/Mobile solution for the Intel Pentium P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system.
The SiS5591/SiS5592 A.G.P./PCI controller integrated the Host-to-PCI bridge, the L2 cache controller, the DRAM controller, the Accelerated Graphics Port interface, and the PCI IDE controller. The L2 cache controller can support up to 1 M P.B. SRAM, and the DRAM controller can support EDO/FP/SDRAM memory up to 768 MB with optional ECC or parity check function. The A.G.P. 1.
SiS5591 Datasheet
