TH50VSF3681AASB Datasheet (Toshiba Semiconductor) - SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

TH50VSF3681AASB, SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

The TH50VSF3680/3681AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a 67,108,864-bit flash memory.

The CIOS and CIOF inputs can be used to select the optimal memory configuration.

The power supply.

FLASH MEMORY a Simultaneous Read/Write operation so that data can be

TH50VSF3681AASB Features

* Power supply voltage VCCs = 2.7 V~3.3 V VCCf = 2.7 V~3.3 V Data retention supply voltage VCCs = 1.5 V~3.3 V Current consumption Operating: 45 mA maximum (CMOS level) Standby: 10 µA maximum (SRAM CMOS level) Standby: 10 µA maximum (FLASH) Block erase architecture for fla