EDI7F328XDNSN Datasheet - White Electronic Designs

EDI7F328XDNSN 8M x 32 / 2 x 8Mx 32 INTEL J3 BASED

The EDI7F328XDNSN and EDI7F2328XDNSN are organized as one and two banks of 8M x 32 respectively. The modules are based on Intel’s E28F640J3, 8M x 8 / 4M x 16 device family. Both modules offer access times of 120-150ns. PIN CONFIGURATIONS PIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 .

EDI7F328XDNSN Features

* 8M x 32 and 2 x 8M x 32 Densities Based on Intel’s Strataﬂash (J3) family of Flash Devices

* E28F640J3 (64) 128Kb Erase Blocks (Symetrical) High Performance Interface Async Page Mode Reads

* 120/25 ns Read Access Time 2.7V - 3.6V Vcc Operation 128 bit Protection Register;

* 6

EDI7F328XDNSN Datasheet (144.53 KB)