ZL30406 Datasheet - Zarlink

ZL30406, SONET/SDH Clock Multiplier PLL

ZL30406 SONET/SDH Clock Multiplier PLL Data Sheet .
The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) a.

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Datasheet Details

Part number:

ZL30406

Manufacturer:

Zarlink

File Size:

307.93 KB

Description:

SONET/SDH Clock Multiplier PLL

Features

* Meets jitter requirements of Telcordia GR-253CORE for OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 77.76 MHz Provides a CML differential clock programm

Applications

* SONET/SDH line cards Network Element timing cards LPF C77oEN-A C77oEN-B OC-CLKoEN C77o ,C155o C19o, C38o, CML-P/N outputs OC-CLKoP/N C19i Frequency & Phase Detector 19.44MHz BIAS Reference & Bias circuit Loop Filter Output VCO Interface Circuit C77oP/N-A C77oP/N-B C77oP/N

ZL30406 Distributors

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ZL30406 SONET SDH Clock Multiplier PLL Zarlink

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