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ZL30415 SONET/SDH Clock Multiplier PLL

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Description

www.DataSheet4U.com ZL30415 SONET/SDH Clock Multiplier PLL Data Sheet .
The ZL30415 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) a.

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Datasheet Specifications

Part number
ZL30415
Manufacturer
Zarlink Semiconductor
File Size
374.37 KB
Datasheet
ZL30415_ZarlinkSemiconductor.pdf
Description
SONET/SDH Clock Multiplier PLL

Features

* Meets jitter requirements of Telcordia GR-253CORE for OC-12, OC-3, and OC-1 rates Meets jitter requirements of ITU-T G.813 for STM4, and STM-1 rates Provides one differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz Pr

Applications

* SONET/SDH line cards REF_SEL LPF FS3 FS2 FS1 C19o, C38o, C77o, C155o, C622o, LVPECL output C19i Reference Selection MUX Frequency & Phase Detector Loop Filter VCO REFinP/N 19.44 MHz and 77.76 MHz State Machine Reference and Bias Circuit Frequency Dividers and Clock Drivers OC-

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