74LS109A Dual J-K Positive-Edge-Triggered Flip-Flops

Texas Instruments

Description

www.ti.com PACKAGE OPTION ADDENDUM 4-Dec-2021 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan (1) Drawi.

Datasheet Specifications

74LS109A Distributors

📁 Related Datasheet

74LS109 - Dual J-K Flip-Flop (Agere Systems)
74LS10 - TRIPLE 3-INPUT NAND GATE (ON Semiconductor)
74LS107 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops (ETC)
74LS11 - Triple 3-Input AND Gate (Fairchild Semiconductor)
74LS112 - Dual J-K Negative-edge-triggered Flip-Flops (Hitachi Semiconductor)
74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP (Motorola)

📌 All Tags

Texas Instruments 74LS109A-like datasheet