* 1 Dual 1:4 Differential Buffer
* Two Clock Inputs
* Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL
* Eight LVPECL Outputs
* Maximum Clock Frequency: 2 GHz
* Maximum Core Current Consumption: 78 mA
* Very Low Additive Jitter:
CDCLVP2104 Datasheet (1.31 MB)
CDCLVP2104
1.31 MB
High-performance clock buffer.
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CDCLVP2104
SCAS889B
* OCTOBER 2009
* REVISED.
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