SN74SSTVF32852 Datasheet - Texas Instruments

SN74SSTVF32852 24-BIT TO 48-BIT REGISTERED BUFFER

ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications. The SN74SS.

D Member of the Texas Instruments Widebus Family D Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200 D Pinout and Functionality Compatible With JEDEC Standard SSTV32852 D Pinout Optimizes 1U DDR DIMM Layout D 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV32852 in PC2700 DIMM Applications D 1-to-2 Outputs Support Stacked DDR DIMMs D One Device Per DIMM Required D Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Lin.

SN74SSTVF32852-etcTI.pdf