SN74SSTV32852 Datasheet - Texas Instruments

SN74SSTV32852 24-BIT TO 48-BIT REGISTERED BUFFER

ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are register.

D Member of the Texas Instruments Widebus Family D 1-to-2 Outputs Support Stacked DDR DIMMs D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Class II Specifications D Differential Clock (CLK and CLK) Inputs D Supports LVCMOS Switching Levels on the RESET Input SN74SSTV32852 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES361C AUGUST 2001 REVISED FEBRUARY 2003 D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All O.

SN74SSTV32852 Datasheet (418.76 KB)