Part number:
74AUP2G0604
Manufacturer:
File Size:
251.01 KB
Description:
Low-power inverting buffer.
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V to 1.65 V)
* JESD8-7 (1.2 V to 1.95 V)
* JESD8-5 (1.8 V to 2.7 V)
* JESD8-B (2.7 V to 3
74AUP2G0604 Datasheet (251.01 KB)
74AUP2G0604
251.01 KB
Low-power inverting buffer.
📁 Related Datasheet
74AUP2G06 - DUAL INVERTERS
(Diodes)
ADVANCED INFORMATION
74AUP2G06
DUAL INVERTERS WITH OPEN DRAIN OUTPUTS
Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed f.
74AUP2G06 - Low-power dual inverter
(nexperia)
74AUP2G06
Low-power dual inverter with open-drain output
Rev. 8 — 31 January 2022
Product data sheet
1. General description
The 74AUP2G06 provides.
74AUP2G00 - Low-power dual 2-input NAND gate
(NXP)
74AUP2G00
Low-power dual 2-input NAND gate
Rev. 8 — 5 February 2013
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NA.
74AUP2G00 - DUAL NAND GATE
(Diodes)
NEW PRODUCT
74AUP2G00
DUAL NAND GATE
Description
Pin Assignments
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power an.
74AUP2G00 - Low-power dual 2-input NAND gate
(nexperia)
74AUP2G00
Low-power dual 2-input NAND gate
Rev. 11 — 9 June 2022
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NAND .
74AUP2G00-Q100 - Low-power dual 2-input NAND gate
(nexperia)
74AUP2G00-Q100
Low-power dual 2-input NAND gate
Rev. 2 — 9 June 2022
Product data sheet
1. General description
The 74AUP2G00-Q100 provides dual 2-in.
74AUP2G02 - DUAL NOR GATE
(Diodes)
NEW PRODUCT
74AUP2G02
DUAL NOR GATE
Description
Pin Assignments
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and.
74AUP2G02 - Low-power Dual 2-input NOR Gate
(NXP)
74AUP2G02
Low-power dual 2-input NOR gate
Rev. 7 — 4 February 2013
Product data sheet
1. General description
The 74AUP2G02 provides a dual 2-input N.