74AUP2G07 Datasheet PDF (Low-power dual buffer) | Download NXP Semiconductors 74AUP2G07

74AUP2G07 - Low-power dual buffer

Description

The 74AUP2G07 provides two non-inverting buffers with open-drain output.

The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Features

s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Low static-power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept.

Datasheet Details

Part number	74AUP2G07
Manufacturer	NXP Semiconductors
File Size	124.67 KB
Description	Low-power dual buffer
Datasheet	74AUP2G07 Datasheet
Additional preview pages of the 74AUP2G07 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com 74AUP2G07 Low-power dual buffer with open-drain output Rev. 02 — 12 June 2007 Product data sheet 1. General description The 74AUP2G07 provides two non-inverting buffers with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully speciﬁed for partial power-down applications using IOFF.

Published: Aug 31, 2009 |