74AUP2G07 Datasheet, Buffer, nexperia

74AUP2G07 Features

• Buffer
• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Overvoltage tolerant inputs to 3.6 V
• Low n

PDF File Details

Part number:

74AUP2G07

Manufacturer:

nexperia ↗

File Size:

256.34kb

Download:

📄 Datasheet

Description:

Low-power dual buffer. The 74AUP2G07 is a dual buffer with open-drain outputs. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inp

74AUP2G07 Application

• Applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is

TAGS

74AUP2G07

nexperia

📁 Related Datasheet

74AUP2G00 - Low-power dual 2-input NAND gate (NXP)
74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NA.

74AUP2G00 - DUAL NAND GATE (Diodes)
NEW PRODUCT 74AUP2G00 DUAL NAND GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power an.

74AUP2G00 - Low-power dual 2-input NAND gate (nexperia)
74AUP2G00 Low-power dual 2-input NAND gate Rev. 11 — 9 June 2022 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND .

74AUP2G00-Q100 - Low-power dual 2-input NAND gate (nexperia)
74AUP2G00-Q100 Low-power dual 2-input NAND gate Rev. 2 — 9 June 2022 Product data sheet 1. General description The 74AUP2G00-Q100 provides dual 2-in.

74AUP2G02 - DUAL NOR GATE (Diodes)
NEW PRODUCT 74AUP2G02 DUAL NOR GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and.

74AUP2G02 - Low-power Dual 2-input NOR Gate (NXP)
74AUP2G02 Low-power dual 2-input NOR gate Rev. 7 — 4 February 2013 Product data sheet 1. General description The 74AUP2G02 provides a dual 2-input N.

74AUP2G02 - Low-power dual 2-input NOR gate (nexperia)
74AUP2G02 Low-power dual 2-input NOR gate Rev. 9 — 27 July 2021 Product data sheet 1. General description The 74AUP2G02 is a dual 2-input NOR gate. .

74AUP2G04 - Low-power dual inverter (NXP)
74AUP2G04 Low-power dual inverter Rev. 6 — 17 September 2015 Product data sheet 1. General description The 74AUP2G04 provides two inverting buffers..

74AUP2G04 - DUAL INVERTERS (Diodes)
Preliminary Datasheet 74AUP2G04 DUAL INVERTERS Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extend.

74AUP2G04 - Low-power dual inverter (nexperia)
74AUP2G04 Low-power dual inverter Rev. 8 — 31 January 2022 Product data sheet 1. General description The 74AUP2G04 is a dual inverter. Schmitt-trigg.