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M12L128168A-5TG2S - 2M x 16 Bit x 4 Banks Synchronous DRAM

This page provides the datasheet information for the M12L128168A-5TG2S, a member of the M12L128168A 2M x 16 Bit x 4 Banks Synchronous DRAM family.

Datasheet Summary

Description

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128168A (2S) 2M x 16 Bit x 4 Banks Synchronous DRAM.

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Datasheet preview – M12L128168A-5TG2S

Datasheet Details

Part number M12L128168A-5TG2S
Manufacturer ESMT
File Size 785.62 KB
Description 2M x 16 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L128168A-5TG2S Datasheet
Additional preview pages of the M12L128168A-5TG2S datasheet.

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Full PDF Text Transcription

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ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128168A (2S) 2M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128168A-5TG2S M12L128168A-5BG2S M12L128168A-6TG2S M12L128168A-6BG2S M12L128168A-7TG2S M12L128168A-7BG2S Max Freq.
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