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FDC6301N - Dual N-Channel / Digital FET

General Description

These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild 's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Key Features

  • 25 V, 0.22 A continuous, 0.5 A Peak. RDS(ON) = 5 Ω @ VGS= 2.7 V RDS(ON) = 4 Ω @ VGS= 4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model. SOT-23 SuperSOTTM-6 Mark: .301 SuperSOTTM-8 SO-8 SOT-223 SOIC-16.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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July 1997 FDC6301N Dual N-Channel , Digital FET General Description These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild 's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, these N-Channel FET's can replace several digital transistors, with a variety of bias resistors. Features 25 V, 0.22 A continuous, 0.5 A Peak. RDS(ON) = 5 Ω @ VGS= 2.7 V RDS(ON) = 4 Ω @ VGS= 4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness.