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GTLP18T612 - 18-Bit LVTTL/GTLP Universal Bus Transceiver

Datasheet Summary

Description

The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation.

It allows for transparent, latched and clocked modes of data transfer.

Features

  • s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold s BiCMOS technology for low power dissipation s Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs s LVTTL compatible Driver and Control inputs s Flow-through architecture optimizes PCB layout s Open drain on GTLP to support wired-or connecti.

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Datasheet Details

Part number GTLP18T612
Manufacturer Fairchild Semiconductor
File Size 74.88 KB
Description 18-Bit LVTTL/GTLP Universal Bus Transceiver
Datasheet download datasheet GTLP18T612 Datasheet
Additional preview pages of the GTLP18T612 datasheet.

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Full PDF Text Transcription

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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver May 1999 Revised September 1999 GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver General Description The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
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